pmc: GRBM_COUNT         GRBM_GUI_ACTIVE         SQ_CYCLES       SQ_BUSY_CYCLES          SQ_WAVES

pmc: TCC_CYCLE[0]                   TCC_RW_REQ[0]               TCC_HIT[0]                  TCC_MISS[0]  TCC_CYCLE[1]                   TCC_RW_REQ[1]               TCC_HIT[1]                  TCC_MISS[1]  TCC_CYCLE[2]                   TCC_RW_REQ[2]               TCC_HIT[2]                  TCC_MISS[2]  TCC_CYCLE[3]                   TCC_RW_REQ[3]               TCC_HIT[3]                  TCC_MISS[3]  TCC_CYCLE[4]                   TCC_RW_REQ[4]               TCC_HIT[4]                  TCC_MISS[4]  TCC_CYCLE[5]                   TCC_RW_REQ[5]               TCC_HIT[5]                  TCC_MISS[5]  TCC_CYCLE[6]                   TCC_RW_REQ[6]               TCC_HIT[6]                  TCC_MISS[6]  TCC_CYCLE[7]                   TCC_RW_REQ[7]               TCC_HIT[7]                  TCC_MISS[7]  TCC_CYCLE[8]                   TCC_RW_REQ[8]               TCC_HIT[8]                  TCC_MISS[8]  TCC_CYCLE[9]                   TCC_RW_REQ[9]               TCC_HIT[9]                  TCC_MISS[9]  TCC_CYCLE[10]                  TCC_RW_REQ[10]              TCC_HIT[10]                 TCC_MISS[10] TCC_CYCLE[11]                  TCC_RW_REQ[11]              TCC_HIT[11]                 TCC_MISS[11] TCC_CYCLE[12]                  TCC_RW_REQ[12]              TCC_HIT[12]                 TCC_MISS[12] TCC_CYCLE[13]                  TCC_RW_REQ[13]              TCC_HIT[13]                 TCC_MISS[13] TCC_CYCLE[14]                  TCC_RW_REQ[14]              TCC_HIT[14]                 TCC_MISS[14] TCC_CYCLE[15]                  TCC_RW_REQ[15]              TCC_HIT[15]                 TCC_MISS[15]



pmc: TCC_REQ[0]                     TCC_READ[0]                 TCC_WRITE[0]                TCC_ATOMIC[0]   TCC_REQ[1]                     TCC_READ[1]                 TCC_WRITE[1]                TCC_ATOMIC[1]   TCC_REQ[2]                     TCC_READ[2]                 TCC_WRITE[2]                TCC_ATOMIC[2]   TCC_REQ[3]                     TCC_READ[3]                 TCC_WRITE[3]                TCC_ATOMIC[3]   TCC_REQ[4]                     TCC_READ[4]                 TCC_WRITE[4]                TCC_ATOMIC[4]   TCC_REQ[5]                     TCC_READ[5]                 TCC_WRITE[5]                TCC_ATOMIC[5]   TCC_REQ[6]                     TCC_READ[6]                 TCC_WRITE[6]                TCC_ATOMIC[6]   TCC_REQ[7]                     TCC_READ[7]                 TCC_WRITE[7]                TCC_ATOMIC[7]   TCC_REQ[8]                     TCC_READ[8]                 TCC_WRITE[8]                TCC_ATOMIC[8]   TCC_REQ[9]                     TCC_READ[9]                 TCC_WRITE[9]                TCC_ATOMIC[9]   TCC_REQ[10]                    TCC_READ[10]                TCC_WRITE[10]               TCC_ATOMIC[10]  TCC_REQ[11]                    TCC_READ[11]                TCC_WRITE[11]               TCC_ATOMIC[11]  TCC_REQ[12]                    TCC_READ[12]                TCC_WRITE[12]               TCC_ATOMIC[12]  TCC_REQ[13]                    TCC_READ[13]                TCC_WRITE[13]               TCC_ATOMIC[13]  TCC_REQ[14]                    TCC_READ[14]                TCC_WRITE[14]               TCC_ATOMIC[14]  TCC_REQ[15]                    TCC_READ[15]                TCC_WRITE[15]               TCC_ATOMIC[15]



pmc: TCC_EA0_RDREQ[0]                TCC_EA0_RDREQ_32B[0]         TCC_EA0_WRREQ[0]             TCC_EA0_WRREQ_64B[0]   TCC_EA0_RDREQ[1]                TCC_EA0_RDREQ_32B[1]         TCC_EA0_WRREQ[1]             TCC_EA0_WRREQ_64B[1]   TCC_EA0_RDREQ[2]                TCC_EA0_RDREQ_32B[2]         TCC_EA0_WRREQ[2]             TCC_EA0_WRREQ_64B[2]   TCC_EA0_RDREQ[3]                TCC_EA0_RDREQ_32B[3]         TCC_EA0_WRREQ[3]             TCC_EA0_WRREQ_64B[3]   TCC_EA0_RDREQ[4]                TCC_EA0_RDREQ_32B[4]         TCC_EA0_WRREQ[4]             TCC_EA0_WRREQ_64B[4]   TCC_EA0_RDREQ[5]                TCC_EA0_RDREQ_32B[5]         TCC_EA0_WRREQ[5]             TCC_EA0_WRREQ_64B[5]   TCC_EA0_RDREQ[6]                TCC_EA0_RDREQ_32B[6]         TCC_EA0_WRREQ[6]             TCC_EA0_WRREQ_64B[6]   TCC_EA0_RDREQ[7]                TCC_EA0_RDREQ_32B[7]         TCC_EA0_WRREQ[7]             TCC_EA0_WRREQ_64B[7]   TCC_EA0_RDREQ[8]                TCC_EA0_RDREQ_32B[8]         TCC_EA0_WRREQ[8]             TCC_EA0_WRREQ_64B[8]   TCC_EA0_RDREQ[9]                TCC_EA0_RDREQ_32B[9]         TCC_EA0_WRREQ[9]             TCC_EA0_WRREQ_64B[9]   TCC_EA0_RDREQ[10]               TCC_EA0_RDREQ_32B[10]        TCC_EA0_WRREQ[10]            TCC_EA0_WRREQ_64B[10]  TCC_EA0_RDREQ[11]               TCC_EA0_RDREQ_32B[11]        TCC_EA0_WRREQ[11]            TCC_EA0_WRREQ_64B[11]  TCC_EA0_RDREQ[12]               TCC_EA0_RDREQ_32B[12]        TCC_EA0_WRREQ[12]            TCC_EA0_WRREQ_64B[12]  TCC_EA0_RDREQ[13]               TCC_EA0_RDREQ_32B[13]        TCC_EA0_WRREQ[13]            TCC_EA0_WRREQ_64B[13]  TCC_EA0_RDREQ[14]               TCC_EA0_RDREQ_32B[14]        TCC_EA0_WRREQ[14]            TCC_EA0_WRREQ_64B[14]  TCC_EA0_RDREQ[15]               TCC_EA0_RDREQ_32B[15]        TCC_EA0_WRREQ[15]            TCC_EA0_WRREQ_64B[15]


pmc: TCC_EA0_ATOMIC[0]               TCC_EA0_RDREQ_LEVEL[0]       TCC_EA0_WRREQ_LEVEL[0]       TCC_EA0_ATOMIC_LEVEL[0]  TCC_EA0_ATOMIC[1]               TCC_EA0_RDREQ_LEVEL[1]       TCC_EA0_WRREQ_LEVEL[1]       TCC_EA0_ATOMIC_LEVEL[1]  TCC_EA0_ATOMIC[2]               TCC_EA0_RDREQ_LEVEL[2]       TCC_EA0_WRREQ_LEVEL[2]       TCC_EA0_ATOMIC_LEVEL[2]  TCC_EA0_ATOMIC[3]               TCC_EA0_RDREQ_LEVEL[3]       TCC_EA0_WRREQ_LEVEL[3]       TCC_EA0_ATOMIC_LEVEL[3]  TCC_EA0_ATOMIC[4]               TCC_EA0_RDREQ_LEVEL[4]       TCC_EA0_WRREQ_LEVEL[4]       TCC_EA0_ATOMIC_LEVEL[4]  TCC_EA0_ATOMIC[5]               TCC_EA0_RDREQ_LEVEL[5]       TCC_EA0_WRREQ_LEVEL[5]       TCC_EA0_ATOMIC_LEVEL[5]  TCC_EA0_ATOMIC[6]               TCC_EA0_RDREQ_LEVEL[6]       TCC_EA0_WRREQ_LEVEL[6]       TCC_EA0_ATOMIC_LEVEL[6]  TCC_EA0_ATOMIC[7]               TCC_EA0_RDREQ_LEVEL[7]       TCC_EA0_WRREQ_LEVEL[7]       TCC_EA0_ATOMIC_LEVEL[7]  TCC_EA0_ATOMIC[8]               TCC_EA0_RDREQ_LEVEL[8]       TCC_EA0_WRREQ_LEVEL[8]       TCC_EA0_ATOMIC_LEVEL[8]  TCC_EA0_ATOMIC[9]               TCC_EA0_RDREQ_LEVEL[9]       TCC_EA0_WRREQ_LEVEL[9]       TCC_EA0_ATOMIC_LEVEL[9]  TCC_EA0_ATOMIC[10]              TCC_EA0_RDREQ_LEVEL[10]      TCC_EA0_WRREQ_LEVEL[10]      TCC_EA0_ATOMIC_LEVEL[10] TCC_EA0_ATOMIC[11]              TCC_EA0_RDREQ_LEVEL[11]      TCC_EA0_WRREQ_LEVEL[11]      TCC_EA0_ATOMIC_LEVEL[11] TCC_EA0_ATOMIC[12]              TCC_EA0_RDREQ_LEVEL[12]      TCC_EA0_WRREQ_LEVEL[12]      TCC_EA0_ATOMIC_LEVEL[12] TCC_EA0_ATOMIC[13]              TCC_EA0_RDREQ_LEVEL[13]      TCC_EA0_WRREQ_LEVEL[13]      TCC_EA0_ATOMIC_LEVEL[13] TCC_EA0_ATOMIC[14]              TCC_EA0_RDREQ_LEVEL[14]      TCC_EA0_WRREQ_LEVEL[14]      TCC_EA0_ATOMIC_LEVEL[14] TCC_EA0_ATOMIC[15]              TCC_EA0_RDREQ_LEVEL[15]      TCC_EA0_WRREQ_LEVEL[15]      TCC_EA0_ATOMIC_LEVEL[15]

pmc: TCC_TAG_STALL[0]  TCC_BUBBLE[0]  TCC_TOO_MANY_EA_WRREQS_STALL[0]  TCC_TAG_STALL[1]  TCC_BUBBLE[1]  TCC_TOO_MANY_EA_WRREQS_STALL[1]  TCC_TAG_STALL[2] TCC_BUBBLE[2]  TCC_TOO_MANY_EA_WRREQS_STALL[2]  TCC_TAG_STALL[3]  TCC_BUBBLE[3]  TCC_TOO_MANY_EA_WRREQS_STALL[3]  TCC_TAG_STALL[4]  TCC_BUBBLE[4]  TCC_TOO_MANY_EA_WRREQS_STALL[4]  TCC_TAG_STALL[5] TCC_BUBBLE[5]  TCC_TOO_MANY_EA_WRREQS_STALL[5]  TCC_TAG_STALL[6]  TCC_BUBBLE[6]  TCC_TOO_MANY_EA_WRREQS_STALL[6]  TCC_TAG_STALL[7]  TCC_BUBBLE[7]  TCC_TOO_MANY_EA_WRREQS_STALL[7]  TCC_TAG_STALL[8] TCC_BUBBLE[8]  TCC_TOO_MANY_EA_WRREQS_STALL[8]  TCC_TAG_STALL[9]  TCC_BUBBLE[9]  TCC_TOO_MANY_EA_WRREQS_STALL[9]  TCC_TAG_STALL[10]  TCC_BUBBLE[10]  TCC_TOO_MANY_EA_WRREQS_STALL[10]  TCC_TAG_STALL[11]  TCC_BUBBLE[11]  TCC_TOO_MANY_EA_WRREQS_STALL[11]  TCC_TAG_STALL[12] TCC_BUBBLE[12]  TCC_TOO_MANY_EA_WRREQS_STALL[12] TCC_TAG_STALL[13]  TCC_BUBBLE[13]  TCC_TOO_MANY_EA_WRREQS_STALL[13]  TCC_TAG_STALL[14]  TCC_BUBBLE[14]  TCC_TOO_MANY_EA_WRREQS_STALL[14]  TCC_TAG_STALL[15] TCC_BUBBLE[15]  TCC_TOO_MANY_EA_WRREQS_STALL[15]



gpu: 
kernel: 
range: 
