pmc: GRBM_COUNT         GRBM_GUI_ACTIVE         SQ_CYCLES       SQ_BUSY_CYCLES          SQ_WAVES

pmc: TCC_CYCLE[0]                   TCC_RW_REQ[0]               TCC_HIT[0]                  TCC_MISS[0]  TCC_CYCLE[1]                   TCC_RW_REQ[1]               TCC_HIT[1]                  TCC_MISS[1]  TCC_CYCLE[2]                   TCC_RW_REQ[2]               TCC_HIT[2]                  TCC_MISS[2]  TCC_CYCLE[3]                   TCC_RW_REQ[3]               TCC_HIT[3]                  TCC_MISS[3]  TCC_CYCLE[4]                   TCC_RW_REQ[4]               TCC_HIT[4]                  TCC_MISS[4]  TCC_CYCLE[5]                   TCC_RW_REQ[5]               TCC_HIT[5]                  TCC_MISS[5]  TCC_CYCLE[6]                   TCC_RW_REQ[6]               TCC_HIT[6]                  TCC_MISS[6]  TCC_CYCLE[7]                   TCC_RW_REQ[7]               TCC_HIT[7]                  TCC_MISS[7]  TCC_CYCLE[8]                   TCC_RW_REQ[8]               TCC_HIT[8]                  TCC_MISS[8]  TCC_CYCLE[9]                   TCC_RW_REQ[9]               TCC_HIT[9]                  TCC_MISS[9]  TCC_CYCLE[10]                  TCC_RW_REQ[10]              TCC_HIT[10]                 TCC_MISS[10] TCC_CYCLE[11]                  TCC_RW_REQ[11]              TCC_HIT[11]                 TCC_MISS[11] TCC_CYCLE[12]                  TCC_RW_REQ[12]              TCC_HIT[12]                 TCC_MISS[12] TCC_CYCLE[13]                  TCC_RW_REQ[13]              TCC_HIT[13]                 TCC_MISS[13] TCC_CYCLE[14]                  TCC_RW_REQ[14]              TCC_HIT[14]                 TCC_MISS[14] TCC_CYCLE[15]                  TCC_RW_REQ[15]              TCC_HIT[15]                 TCC_MISS[15] TCC_CYCLE[16]                  TCC_RW_REQ[16]              TCC_HIT[16]                 TCC_MISS[16] TCC_CYCLE[17]                  TCC_RW_REQ[17]              TCC_HIT[17]                 TCC_MISS[17] TCC_CYCLE[18]                  TCC_RW_REQ[18]              TCC_HIT[18]                 TCC_MISS[18] TCC_CYCLE[19]                  TCC_RW_REQ[19]              TCC_HIT[19]                 TCC_MISS[19] TCC_CYCLE[20]                  TCC_RW_REQ[20]              TCC_HIT[20]                 TCC_MISS[20] TCC_CYCLE[21]                  TCC_RW_REQ[21]              TCC_HIT[21]                 TCC_MISS[21] TCC_CYCLE[22]                  TCC_RW_REQ[22]              TCC_HIT[22]                 TCC_MISS[22] TCC_CYCLE[23]                  TCC_RW_REQ[23]              TCC_HIT[23]                 TCC_MISS[23] TCC_CYCLE[24]                  TCC_RW_REQ[24]              TCC_HIT[24]                 TCC_MISS[24] TCC_CYCLE[25]                  TCC_RW_REQ[25]              TCC_HIT[25]                 TCC_MISS[25] TCC_CYCLE[26]                  TCC_RW_REQ[26]              TCC_HIT[26]                 TCC_MISS[26] TCC_CYCLE[27]                  TCC_RW_REQ[27]              TCC_HIT[27]                 TCC_MISS[27] TCC_CYCLE[28]                  TCC_RW_REQ[28]              TCC_HIT[28]                 TCC_MISS[28] TCC_CYCLE[29]                  TCC_RW_REQ[29]              TCC_HIT[29]                 TCC_MISS[29] TCC_CYCLE[30]                  TCC_RW_REQ[30]              TCC_HIT[30]                 TCC_MISS[30] TCC_CYCLE[31]                  TCC_RW_REQ[31]              TCC_HIT[31]                 TCC_MISS[31] 



pmc: TCC_REQ[0]                     TCC_READ[0]                 TCC_WRITE[0]                TCC_ATOMIC[0]   TCC_REQ[1]                     TCC_READ[1]                 TCC_WRITE[1]                TCC_ATOMIC[1]   TCC_REQ[2]                     TCC_READ[2]                 TCC_WRITE[2]                TCC_ATOMIC[2]   TCC_REQ[3]                     TCC_READ[3]                 TCC_WRITE[3]                TCC_ATOMIC[3]   TCC_REQ[4]                     TCC_READ[4]                 TCC_WRITE[4]                TCC_ATOMIC[4]   TCC_REQ[5]                     TCC_READ[5]                 TCC_WRITE[5]                TCC_ATOMIC[5]   TCC_REQ[6]                     TCC_READ[6]                 TCC_WRITE[6]                TCC_ATOMIC[6]   TCC_REQ[7]                     TCC_READ[7]                 TCC_WRITE[7]                TCC_ATOMIC[7]   TCC_REQ[8]                     TCC_READ[8]                 TCC_WRITE[8]                TCC_ATOMIC[8]   TCC_REQ[9]                     TCC_READ[9]                 TCC_WRITE[9]                TCC_ATOMIC[9]   TCC_REQ[10]                    TCC_READ[10]                TCC_WRITE[10]               TCC_ATOMIC[10]  TCC_REQ[11]                    TCC_READ[11]                TCC_WRITE[11]               TCC_ATOMIC[11]  TCC_REQ[12]                    TCC_READ[12]                TCC_WRITE[12]               TCC_ATOMIC[12]  TCC_REQ[13]                    TCC_READ[13]                TCC_WRITE[13]               TCC_ATOMIC[13]  TCC_REQ[14]                    TCC_READ[14]                TCC_WRITE[14]               TCC_ATOMIC[14]  TCC_REQ[15]                    TCC_READ[15]                TCC_WRITE[15]               TCC_ATOMIC[15]  TCC_REQ[16]                    TCC_READ[16]                TCC_WRITE[16]               TCC_ATOMIC[16]  TCC_REQ[17]                    TCC_READ[17]                TCC_WRITE[17]               TCC_ATOMIC[17]  TCC_REQ[18]                    TCC_READ[18]                TCC_WRITE[18]               TCC_ATOMIC[18]  TCC_REQ[19]                    TCC_READ[19]                TCC_WRITE[19]               TCC_ATOMIC[19]  TCC_REQ[20]                    TCC_READ[20]                TCC_WRITE[20]               TCC_ATOMIC[20]  TCC_REQ[21]                    TCC_READ[21]                TCC_WRITE[21]               TCC_ATOMIC[21]  TCC_REQ[22]                    TCC_READ[22]                TCC_WRITE[22]               TCC_ATOMIC[22]  TCC_REQ[23]                    TCC_READ[23]                TCC_WRITE[23]               TCC_ATOMIC[23]  TCC_REQ[24]                    TCC_READ[24]                TCC_WRITE[24]               TCC_ATOMIC[24]  TCC_REQ[25]                    TCC_READ[25]                TCC_WRITE[25]               TCC_ATOMIC[25]  TCC_REQ[26]                    TCC_READ[26]                TCC_WRITE[26]               TCC_ATOMIC[26]  TCC_REQ[27]                    TCC_READ[27]                TCC_WRITE[27]               TCC_ATOMIC[27]  TCC_REQ[28]                    TCC_READ[28]                TCC_WRITE[28]               TCC_ATOMIC[28]  TCC_REQ[29]                    TCC_READ[29]                TCC_WRITE[29]               TCC_ATOMIC[29]  TCC_REQ[30]                    TCC_READ[30]                TCC_WRITE[30]               TCC_ATOMIC[30]  TCC_REQ[31]                    TCC_READ[31]                TCC_WRITE[31]               TCC_ATOMIC[31]  



pmc: TCC_EA_RDREQ[0]                TCC_EA_RDREQ_32B[0]         TCC_EA_WRREQ[0]             TCC_EA_WRREQ_64B[0]   TCC_EA_RDREQ[1]                TCC_EA_RDREQ_32B[1]         TCC_EA_WRREQ[1]             TCC_EA_WRREQ_64B[1]   TCC_EA_RDREQ[2]                TCC_EA_RDREQ_32B[2]         TCC_EA_WRREQ[2]             TCC_EA_WRREQ_64B[2]   TCC_EA_RDREQ[3]                TCC_EA_RDREQ_32B[3]         TCC_EA_WRREQ[3]             TCC_EA_WRREQ_64B[3]   TCC_EA_RDREQ[4]                TCC_EA_RDREQ_32B[4]         TCC_EA_WRREQ[4]             TCC_EA_WRREQ_64B[4]   TCC_EA_RDREQ[5]                TCC_EA_RDREQ_32B[5]         TCC_EA_WRREQ[5]             TCC_EA_WRREQ_64B[5]   TCC_EA_RDREQ[6]                TCC_EA_RDREQ_32B[6]         TCC_EA_WRREQ[6]             TCC_EA_WRREQ_64B[6]   TCC_EA_RDREQ[7]                TCC_EA_RDREQ_32B[7]         TCC_EA_WRREQ[7]             TCC_EA_WRREQ_64B[7]   TCC_EA_RDREQ[8]                TCC_EA_RDREQ_32B[8]         TCC_EA_WRREQ[8]             TCC_EA_WRREQ_64B[8]   TCC_EA_RDREQ[9]                TCC_EA_RDREQ_32B[9]         TCC_EA_WRREQ[9]             TCC_EA_WRREQ_64B[9]   TCC_EA_RDREQ[10]               TCC_EA_RDREQ_32B[10]        TCC_EA_WRREQ[10]            TCC_EA_WRREQ_64B[10]  TCC_EA_RDREQ[11]               TCC_EA_RDREQ_32B[11]        TCC_EA_WRREQ[11]            TCC_EA_WRREQ_64B[11]  TCC_EA_RDREQ[12]               TCC_EA_RDREQ_32B[12]        TCC_EA_WRREQ[12]            TCC_EA_WRREQ_64B[12]  TCC_EA_RDREQ[13]               TCC_EA_RDREQ_32B[13]        TCC_EA_WRREQ[13]            TCC_EA_WRREQ_64B[13]  TCC_EA_RDREQ[14]               TCC_EA_RDREQ_32B[14]        TCC_EA_WRREQ[14]            TCC_EA_WRREQ_64B[14]  TCC_EA_RDREQ[15]               TCC_EA_RDREQ_32B[15]        TCC_EA_WRREQ[15]            TCC_EA_WRREQ_64B[15]  TCC_EA_RDREQ[16]               TCC_EA_RDREQ_32B[16]        TCC_EA_WRREQ[16]            TCC_EA_WRREQ_64B[16]  TCC_EA_RDREQ[17]               TCC_EA_RDREQ_32B[17]        TCC_EA_WRREQ[17]            TCC_EA_WRREQ_64B[17]  TCC_EA_RDREQ[18]               TCC_EA_RDREQ_32B[18]        TCC_EA_WRREQ[18]            TCC_EA_WRREQ_64B[18]  TCC_EA_RDREQ[19]               TCC_EA_RDREQ_32B[19]        TCC_EA_WRREQ[19]            TCC_EA_WRREQ_64B[19]  TCC_EA_RDREQ[20]               TCC_EA_RDREQ_32B[20]        TCC_EA_WRREQ[20]            TCC_EA_WRREQ_64B[20]  TCC_EA_RDREQ[21]               TCC_EA_RDREQ_32B[21]        TCC_EA_WRREQ[21]            TCC_EA_WRREQ_64B[21]  TCC_EA_RDREQ[22]               TCC_EA_RDREQ_32B[22]        TCC_EA_WRREQ[22]            TCC_EA_WRREQ_64B[22]  TCC_EA_RDREQ[23]               TCC_EA_RDREQ_32B[23]        TCC_EA_WRREQ[23]            TCC_EA_WRREQ_64B[23]  TCC_EA_RDREQ[24]               TCC_EA_RDREQ_32B[24]        TCC_EA_WRREQ[24]            TCC_EA_WRREQ_64B[24]  TCC_EA_RDREQ[25]               TCC_EA_RDREQ_32B[25]        TCC_EA_WRREQ[25]            TCC_EA_WRREQ_64B[25]  TCC_EA_RDREQ[26]               TCC_EA_RDREQ_32B[26]        TCC_EA_WRREQ[26]            TCC_EA_WRREQ_64B[26]  TCC_EA_RDREQ[27]               TCC_EA_RDREQ_32B[27]        TCC_EA_WRREQ[27]            TCC_EA_WRREQ_64B[27]  TCC_EA_RDREQ[28]               TCC_EA_RDREQ_32B[28]        TCC_EA_WRREQ[28]            TCC_EA_WRREQ_64B[28]  TCC_EA_RDREQ[29]               TCC_EA_RDREQ_32B[29]        TCC_EA_WRREQ[29]            TCC_EA_WRREQ_64B[29]  TCC_EA_RDREQ[30]               TCC_EA_RDREQ_32B[30]        TCC_EA_WRREQ[30]            TCC_EA_WRREQ_64B[30]  TCC_EA_RDREQ[31]               TCC_EA_RDREQ_32B[31]        TCC_EA_WRREQ[31]            TCC_EA_WRREQ_64B[31]  


pmc: TCC_EA_ATOMIC[0]               TCC_EA_RDREQ_LEVEL[0]       TCC_EA_WRREQ_LEVEL[0]       TCC_EA_ATOMIC_LEVEL[0]  TCC_EA_ATOMIC[1]               TCC_EA_RDREQ_LEVEL[1]       TCC_EA_WRREQ_LEVEL[1]       TCC_EA_ATOMIC_LEVEL[1]  TCC_EA_ATOMIC[2]               TCC_EA_RDREQ_LEVEL[2]       TCC_EA_WRREQ_LEVEL[2]       TCC_EA_ATOMIC_LEVEL[2]  TCC_EA_ATOMIC[3]               TCC_EA_RDREQ_LEVEL[3]       TCC_EA_WRREQ_LEVEL[3]       TCC_EA_ATOMIC_LEVEL[3]  TCC_EA_ATOMIC[4]               TCC_EA_RDREQ_LEVEL[4]       TCC_EA_WRREQ_LEVEL[4]       TCC_EA_ATOMIC_LEVEL[4]  TCC_EA_ATOMIC[5]               TCC_EA_RDREQ_LEVEL[5]       TCC_EA_WRREQ_LEVEL[5]       TCC_EA_ATOMIC_LEVEL[5]  TCC_EA_ATOMIC[6]               TCC_EA_RDREQ_LEVEL[6]       TCC_EA_WRREQ_LEVEL[6]       TCC_EA_ATOMIC_LEVEL[6]  TCC_EA_ATOMIC[7]               TCC_EA_RDREQ_LEVEL[7]       TCC_EA_WRREQ_LEVEL[7]       TCC_EA_ATOMIC_LEVEL[7]  TCC_EA_ATOMIC[8]               TCC_EA_RDREQ_LEVEL[8]       TCC_EA_WRREQ_LEVEL[8]       TCC_EA_ATOMIC_LEVEL[8]  TCC_EA_ATOMIC[9]               TCC_EA_RDREQ_LEVEL[9]       TCC_EA_WRREQ_LEVEL[9]       TCC_EA_ATOMIC_LEVEL[9]  TCC_EA_ATOMIC[10]              TCC_EA_RDREQ_LEVEL[10]      TCC_EA_WRREQ_LEVEL[10]      TCC_EA_ATOMIC_LEVEL[10] TCC_EA_ATOMIC[11]              TCC_EA_RDREQ_LEVEL[11]      TCC_EA_WRREQ_LEVEL[11]      TCC_EA_ATOMIC_LEVEL[11] TCC_EA_ATOMIC[12]              TCC_EA_RDREQ_LEVEL[12]      TCC_EA_WRREQ_LEVEL[12]      TCC_EA_ATOMIC_LEVEL[12] TCC_EA_ATOMIC[13]              TCC_EA_RDREQ_LEVEL[13]      TCC_EA_WRREQ_LEVEL[13]      TCC_EA_ATOMIC_LEVEL[13] TCC_EA_ATOMIC[14]              TCC_EA_RDREQ_LEVEL[14]      TCC_EA_WRREQ_LEVEL[14]      TCC_EA_ATOMIC_LEVEL[14] TCC_EA_ATOMIC[15]              TCC_EA_RDREQ_LEVEL[15]      TCC_EA_WRREQ_LEVEL[15]      TCC_EA_ATOMIC_LEVEL[15] TCC_EA_ATOMIC[16]              TCC_EA_RDREQ_LEVEL[16]      TCC_EA_WRREQ_LEVEL[16]      TCC_EA_ATOMIC_LEVEL[16] TCC_EA_ATOMIC[17]              TCC_EA_RDREQ_LEVEL[17]      TCC_EA_WRREQ_LEVEL[17]      TCC_EA_ATOMIC_LEVEL[17] TCC_EA_ATOMIC[18]              TCC_EA_RDREQ_LEVEL[18]      TCC_EA_WRREQ_LEVEL[18]      TCC_EA_ATOMIC_LEVEL[18] TCC_EA_ATOMIC[19]              TCC_EA_RDREQ_LEVEL[19]      TCC_EA_WRREQ_LEVEL[19]      TCC_EA_ATOMIC_LEVEL[19] TCC_EA_ATOMIC[20]              TCC_EA_RDREQ_LEVEL[20]      TCC_EA_WRREQ_LEVEL[20]      TCC_EA_ATOMIC_LEVEL[20] TCC_EA_ATOMIC[21]              TCC_EA_RDREQ_LEVEL[21]      TCC_EA_WRREQ_LEVEL[21]      TCC_EA_ATOMIC_LEVEL[21] TCC_EA_ATOMIC[22]              TCC_EA_RDREQ_LEVEL[22]      TCC_EA_WRREQ_LEVEL[22]      TCC_EA_ATOMIC_LEVEL[22] TCC_EA_ATOMIC[23]              TCC_EA_RDREQ_LEVEL[23]      TCC_EA_WRREQ_LEVEL[23]      TCC_EA_ATOMIC_LEVEL[23] TCC_EA_ATOMIC[24]              TCC_EA_RDREQ_LEVEL[24]      TCC_EA_WRREQ_LEVEL[24]      TCC_EA_ATOMIC_LEVEL[24] TCC_EA_ATOMIC[25]              TCC_EA_RDREQ_LEVEL[25]      TCC_EA_WRREQ_LEVEL[25]      TCC_EA_ATOMIC_LEVEL[25] TCC_EA_ATOMIC[26]              TCC_EA_RDREQ_LEVEL[26]      TCC_EA_WRREQ_LEVEL[26]      TCC_EA_ATOMIC_LEVEL[26] TCC_EA_ATOMIC[27]              TCC_EA_RDREQ_LEVEL[27]      TCC_EA_WRREQ_LEVEL[27]      TCC_EA_ATOMIC_LEVEL[27] TCC_EA_ATOMIC[28]              TCC_EA_RDREQ_LEVEL[28]      TCC_EA_WRREQ_LEVEL[28]      TCC_EA_ATOMIC_LEVEL[28] TCC_EA_ATOMIC[29]              TCC_EA_RDREQ_LEVEL[29]      TCC_EA_WRREQ_LEVEL[29]      TCC_EA_ATOMIC_LEVEL[29] TCC_EA_ATOMIC[30]              TCC_EA_RDREQ_LEVEL[30]      TCC_EA_WRREQ_LEVEL[30]      TCC_EA_ATOMIC_LEVEL[30] TCC_EA_ATOMIC[31]              TCC_EA_RDREQ_LEVEL[31]      TCC_EA_WRREQ_LEVEL[31]      TCC_EA_ATOMIC_LEVEL[31] 




pmc: TCC_EA_RDREQ_IO_CREDIT_STALL[0]   TCC_EA_RDREQ_GMI_CREDIT_STALL[0]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[0]  TCC_EA_RDREQ_IO_CREDIT_STALL[1]   TCC_EA_RDREQ_GMI_CREDIT_STALL[1]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[1]  TCC_EA_RDREQ_IO_CREDIT_STALL[2]   TCC_EA_RDREQ_GMI_CREDIT_STALL[2]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[2]  TCC_EA_RDREQ_IO_CREDIT_STALL[3]   TCC_EA_RDREQ_GMI_CREDIT_STALL[3]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[3]  TCC_EA_RDREQ_IO_CREDIT_STALL[4]   TCC_EA_RDREQ_GMI_CREDIT_STALL[4]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[4]  TCC_EA_RDREQ_IO_CREDIT_STALL[5]   TCC_EA_RDREQ_GMI_CREDIT_STALL[5]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[5]  TCC_EA_RDREQ_IO_CREDIT_STALL[6]   TCC_EA_RDREQ_GMI_CREDIT_STALL[6]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[6]  TCC_EA_RDREQ_IO_CREDIT_STALL[7]   TCC_EA_RDREQ_GMI_CREDIT_STALL[7]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[7]  TCC_EA_RDREQ_IO_CREDIT_STALL[8]   TCC_EA_RDREQ_GMI_CREDIT_STALL[8]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[8]  TCC_EA_RDREQ_IO_CREDIT_STALL[9]   TCC_EA_RDREQ_GMI_CREDIT_STALL[9]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[9]  TCC_EA_RDREQ_IO_CREDIT_STALL[10]  TCC_EA_RDREQ_GMI_CREDIT_STALL[10] TCC_EA_RDREQ_DRAM_CREDIT_STALL[10] TCC_EA_RDREQ_IO_CREDIT_STALL[11]  TCC_EA_RDREQ_GMI_CREDIT_STALL[11] TCC_EA_RDREQ_DRAM_CREDIT_STALL[11] TCC_EA_RDREQ_IO_CREDIT_STALL[12]  TCC_EA_RDREQ_GMI_CREDIT_STALL[12] TCC_EA_RDREQ_DRAM_CREDIT_STALL[12] TCC_EA_RDREQ_IO_CREDIT_STALL[13]  TCC_EA_RDREQ_GMI_CREDIT_STALL[13] TCC_EA_RDREQ_DRAM_CREDIT_STALL[13] TCC_EA_RDREQ_IO_CREDIT_STALL[14]  TCC_EA_RDREQ_GMI_CREDIT_STALL[14] TCC_EA_RDREQ_DRAM_CREDIT_STALL[14] TCC_EA_RDREQ_IO_CREDIT_STALL[15]  TCC_EA_RDREQ_GMI_CREDIT_STALL[15] TCC_EA_RDREQ_DRAM_CREDIT_STALL[15] TCC_EA_RDREQ_IO_CREDIT_STALL[16]  TCC_EA_RDREQ_GMI_CREDIT_STALL[16] TCC_EA_RDREQ_DRAM_CREDIT_STALL[16] TCC_EA_RDREQ_IO_CREDIT_STALL[17]  TCC_EA_RDREQ_GMI_CREDIT_STALL[17] TCC_EA_RDREQ_DRAM_CREDIT_STALL[17] TCC_EA_RDREQ_IO_CREDIT_STALL[18]  TCC_EA_RDREQ_GMI_CREDIT_STALL[18] TCC_EA_RDREQ_DRAM_CREDIT_STALL[18] TCC_EA_RDREQ_IO_CREDIT_STALL[19]  TCC_EA_RDREQ_GMI_CREDIT_STALL[19] TCC_EA_RDREQ_DRAM_CREDIT_STALL[19] TCC_EA_RDREQ_IO_CREDIT_STALL[20]  TCC_EA_RDREQ_GMI_CREDIT_STALL[20] TCC_EA_RDREQ_DRAM_CREDIT_STALL[20] TCC_EA_RDREQ_IO_CREDIT_STALL[21]  TCC_EA_RDREQ_GMI_CREDIT_STALL[21] TCC_EA_RDREQ_DRAM_CREDIT_STALL[21] TCC_EA_RDREQ_IO_CREDIT_STALL[22]  TCC_EA_RDREQ_GMI_CREDIT_STALL[22] TCC_EA_RDREQ_DRAM_CREDIT_STALL[22] TCC_EA_RDREQ_IO_CREDIT_STALL[23]  TCC_EA_RDREQ_GMI_CREDIT_STALL[23] TCC_EA_RDREQ_DRAM_CREDIT_STALL[23] TCC_EA_RDREQ_IO_CREDIT_STALL[24]  TCC_EA_RDREQ_GMI_CREDIT_STALL[24] TCC_EA_RDREQ_DRAM_CREDIT_STALL[24] TCC_EA_RDREQ_IO_CREDIT_STALL[25]  TCC_EA_RDREQ_GMI_CREDIT_STALL[25] TCC_EA_RDREQ_DRAM_CREDIT_STALL[25] TCC_EA_RDREQ_IO_CREDIT_STALL[26]  TCC_EA_RDREQ_GMI_CREDIT_STALL[26] TCC_EA_RDREQ_DRAM_CREDIT_STALL[26] TCC_EA_RDREQ_IO_CREDIT_STALL[27]  TCC_EA_RDREQ_GMI_CREDIT_STALL[27] TCC_EA_RDREQ_DRAM_CREDIT_STALL[27] TCC_EA_RDREQ_IO_CREDIT_STALL[28]  TCC_EA_RDREQ_GMI_CREDIT_STALL[28] TCC_EA_RDREQ_DRAM_CREDIT_STALL[28] TCC_EA_RDREQ_IO_CREDIT_STALL[29]  TCC_EA_RDREQ_GMI_CREDIT_STALL[29] TCC_EA_RDREQ_DRAM_CREDIT_STALL[29] TCC_EA_RDREQ_IO_CREDIT_STALL[30]  TCC_EA_RDREQ_GMI_CREDIT_STALL[30] TCC_EA_RDREQ_DRAM_CREDIT_STALL[30] TCC_EA_RDREQ_IO_CREDIT_STALL[31]  TCC_EA_RDREQ_GMI_CREDIT_STALL[31] TCC_EA_RDREQ_DRAM_CREDIT_STALL[31] 


pmc: TCC_EA_WRREQ_IO_CREDIT_STALL[0]   TCC_EA_WRREQ_GMI_CREDIT_STALL[0]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[0]  TCC_TOO_MANY_EA_WRREQS_STALL[0] TCC_EA_WRREQ_IO_CREDIT_STALL[1]   TCC_EA_WRREQ_GMI_CREDIT_STALL[1]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[1]  TCC_TOO_MANY_EA_WRREQS_STALL[1] TCC_EA_WRREQ_IO_CREDIT_STALL[2]   TCC_EA_WRREQ_GMI_CREDIT_STALL[2]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[2]  TCC_TOO_MANY_EA_WRREQS_STALL[2] TCC_EA_WRREQ_IO_CREDIT_STALL[3]   TCC_EA_WRREQ_GMI_CREDIT_STALL[3]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[3]  TCC_TOO_MANY_EA_WRREQS_STALL[3] TCC_EA_WRREQ_IO_CREDIT_STALL[4]   TCC_EA_WRREQ_GMI_CREDIT_STALL[4]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[4]  TCC_TOO_MANY_EA_WRREQS_STALL[4] TCC_EA_WRREQ_IO_CREDIT_STALL[5]   TCC_EA_WRREQ_GMI_CREDIT_STALL[5]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[5]  TCC_TOO_MANY_EA_WRREQS_STALL[5] TCC_EA_WRREQ_IO_CREDIT_STALL[6]   TCC_EA_WRREQ_GMI_CREDIT_STALL[6]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[6]  TCC_TOO_MANY_EA_WRREQS_STALL[6] TCC_EA_WRREQ_IO_CREDIT_STALL[7]   TCC_EA_WRREQ_GMI_CREDIT_STALL[7]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[7]  TCC_TOO_MANY_EA_WRREQS_STALL[7] TCC_EA_WRREQ_IO_CREDIT_STALL[8]   TCC_EA_WRREQ_GMI_CREDIT_STALL[8]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[8]  TCC_TOO_MANY_EA_WRREQS_STALL[8] TCC_EA_WRREQ_IO_CREDIT_STALL[9]   TCC_EA_WRREQ_GMI_CREDIT_STALL[9]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[9]  TCC_TOO_MANY_EA_WRREQS_STALL[9] TCC_EA_WRREQ_IO_CREDIT_STALL[10]  TCC_EA_WRREQ_GMI_CREDIT_STALL[10] TCC_EA_WRREQ_DRAM_CREDIT_STALL[10] TCC_TOO_MANY_EA_WRREQS_STALL[10] TCC_EA_WRREQ_IO_CREDIT_STALL[11]  TCC_EA_WRREQ_GMI_CREDIT_STALL[11] TCC_EA_WRREQ_DRAM_CREDIT_STALL[11] TCC_TOO_MANY_EA_WRREQS_STALL[11] TCC_EA_WRREQ_IO_CREDIT_STALL[12]  TCC_EA_WRREQ_GMI_CREDIT_STALL[12] TCC_EA_WRREQ_DRAM_CREDIT_STALL[12] TCC_TOO_MANY_EA_WRREQS_STALL[12] TCC_EA_WRREQ_IO_CREDIT_STALL[13]  TCC_EA_WRREQ_GMI_CREDIT_STALL[13] TCC_EA_WRREQ_DRAM_CREDIT_STALL[13] TCC_TOO_MANY_EA_WRREQS_STALL[13] TCC_EA_WRREQ_IO_CREDIT_STALL[14]  TCC_EA_WRREQ_GMI_CREDIT_STALL[14] TCC_EA_WRREQ_DRAM_CREDIT_STALL[14] TCC_TOO_MANY_EA_WRREQS_STALL[14] TCC_EA_WRREQ_IO_CREDIT_STALL[15]  TCC_EA_WRREQ_GMI_CREDIT_STALL[15] TCC_EA_WRREQ_DRAM_CREDIT_STALL[15] TCC_TOO_MANY_EA_WRREQS_STALL[15] TCC_EA_WRREQ_IO_CREDIT_STALL[16]  TCC_EA_WRREQ_GMI_CREDIT_STALL[16] TCC_EA_WRREQ_DRAM_CREDIT_STALL[16] TCC_TOO_MANY_EA_WRREQS_STALL[16] TCC_EA_WRREQ_IO_CREDIT_STALL[17]  TCC_EA_WRREQ_GMI_CREDIT_STALL[17] TCC_EA_WRREQ_DRAM_CREDIT_STALL[17] TCC_TOO_MANY_EA_WRREQS_STALL[17] TCC_EA_WRREQ_IO_CREDIT_STALL[18]  TCC_EA_WRREQ_GMI_CREDIT_STALL[18] TCC_EA_WRREQ_DRAM_CREDIT_STALL[18] TCC_TOO_MANY_EA_WRREQS_STALL[18] TCC_EA_WRREQ_IO_CREDIT_STALL[19]  TCC_EA_WRREQ_GMI_CREDIT_STALL[19] TCC_EA_WRREQ_DRAM_CREDIT_STALL[19] TCC_TOO_MANY_EA_WRREQS_STALL[19] TCC_EA_WRREQ_IO_CREDIT_STALL[20]  TCC_EA_WRREQ_GMI_CREDIT_STALL[20] TCC_EA_WRREQ_DRAM_CREDIT_STALL[20] TCC_TOO_MANY_EA_WRREQS_STALL[20] TCC_EA_WRREQ_IO_CREDIT_STALL[21]  TCC_EA_WRREQ_GMI_CREDIT_STALL[21] TCC_EA_WRREQ_DRAM_CREDIT_STALL[21] TCC_TOO_MANY_EA_WRREQS_STALL[21] TCC_EA_WRREQ_IO_CREDIT_STALL[22]  TCC_EA_WRREQ_GMI_CREDIT_STALL[22] TCC_EA_WRREQ_DRAM_CREDIT_STALL[22] TCC_TOO_MANY_EA_WRREQS_STALL[22] TCC_EA_WRREQ_IO_CREDIT_STALL[23]  TCC_EA_WRREQ_GMI_CREDIT_STALL[23] TCC_EA_WRREQ_DRAM_CREDIT_STALL[23] TCC_TOO_MANY_EA_WRREQS_STALL[23] TCC_EA_WRREQ_IO_CREDIT_STALL[24]  TCC_EA_WRREQ_GMI_CREDIT_STALL[24] TCC_EA_WRREQ_DRAM_CREDIT_STALL[24] TCC_TOO_MANY_EA_WRREQS_STALL[24] TCC_EA_WRREQ_IO_CREDIT_STALL[25]  TCC_EA_WRREQ_GMI_CREDIT_STALL[25] TCC_EA_WRREQ_DRAM_CREDIT_STALL[25] TCC_TOO_MANY_EA_WRREQS_STALL[25] TCC_EA_WRREQ_IO_CREDIT_STALL[26]  TCC_EA_WRREQ_GMI_CREDIT_STALL[26] TCC_EA_WRREQ_DRAM_CREDIT_STALL[26] TCC_TOO_MANY_EA_WRREQS_STALL[26] TCC_EA_WRREQ_IO_CREDIT_STALL[27]  TCC_EA_WRREQ_GMI_CREDIT_STALL[27] TCC_EA_WRREQ_DRAM_CREDIT_STALL[27] TCC_TOO_MANY_EA_WRREQS_STALL[27] TCC_EA_WRREQ_IO_CREDIT_STALL[28]  TCC_EA_WRREQ_GMI_CREDIT_STALL[28] TCC_EA_WRREQ_DRAM_CREDIT_STALL[28] TCC_TOO_MANY_EA_WRREQS_STALL[28] TCC_EA_WRREQ_IO_CREDIT_STALL[29]  TCC_EA_WRREQ_GMI_CREDIT_STALL[29] TCC_EA_WRREQ_DRAM_CREDIT_STALL[29] TCC_TOO_MANY_EA_WRREQS_STALL[29] TCC_EA_WRREQ_IO_CREDIT_STALL[30]  TCC_EA_WRREQ_GMI_CREDIT_STALL[30] TCC_EA_WRREQ_DRAM_CREDIT_STALL[30] TCC_TOO_MANY_EA_WRREQS_STALL[30] TCC_EA_WRREQ_IO_CREDIT_STALL[31]  TCC_EA_WRREQ_GMI_CREDIT_STALL[31] TCC_EA_WRREQ_DRAM_CREDIT_STALL[31] TCC_TOO_MANY_EA_WRREQS_STALL[31]

gpu: 
kernel: 
range: 

